General Information
| HOT CHIPS 7 (1995) | |
|---|---|
| Date | August 13-15, 1995 |
| Place | Memorial Auditorium, Stanford University |
| Program | Final Program  |
| Committees | Not Available |
Conference Day One
| Session | Monday, August 14, 1995 |
|---|---|
| Opening Remarks 09:00-9:15 |
General Chair: Nam Ling Program Co-Chairs: Hasan S. AlKhatib, Norman P. Jouppi |
| Session 1 09:15-10:45 |
Embedded Processors Chair: Robert Garner, Sun Microsystems The First Superscalar 29K™ Family Member, B. McMinn (AMD)
The Architecture of the NS486 Integrated Processor, M. D. Nemirovsky (National Semiconductor) The MiniRISC™ CW4010: A Superscalar MIPS Processor ASIC Core, P. Cobb, J. Cesana (LSI Logic) |
| Keynote 11:15-12:15 |
Nanometers and Gigabucks Gordon Moore, Chairman, Intel Corporation |
| Session 2 13:45-15:15 |
x86 Processors Chair: Mark Horowitz, Stanford University Optimizing the P6 Pipeline, D. Papworth (Intel) AMD-K5™ Microprocessor, D. Christie (AMD) Building a Better Beast: Native vs. RISC-like vs. VLIW Methods of Implementing x86 Microprocessors, T. Garibay (Cyrix) |
| Session 3 15:45-17:15 |
RISC (Part 1) Chair: Winfried W. Wilcke (HaL Computer Systems)Performance Evaluation of the Superscalar Speculative Exectution HaL SPARC64 Processor, A. Essen, S. Goldstein (HaL Computer Systems)
SPARC64™+: HAL’s Second Generation 64-bit SPARC Processor, G.W. Shen (HaL Computer Systems) Memory Performance Features of the 64-bit PA-8000, B. Naas (Hewlett-Packard) |
| Panel Discussion 19:00-21:00 |
What is the Role of Competing Architectures in an x86 World Order? Moderators: John Warton, Consultant/Analyst, Applications Research Panelists: Keith Diefendorff (Motorola) David Ditzel (Transmeta Corp) John Novitsky (Micro-Module Systems) Nick Tredennick (TechNerds International) Pete Wilson (Microsystems Architecture) |
Conference Day Two
| Session | Tuesday, August 15, 1995 |
|---|---|
| Session 4 09:00-10:30 |
MPEG Chair: Vivian Shen, Hewlett-Packard A Two-Chip Real-Time MPEG2 Video Encoder with Wide Range Motion Estimation, T. Kondo, K. Suguri, M. Ikeda, T. Abe, H. Matsuda, T. Okubo, K. Ogura (NTT LSI Laboratories); Y. Tashiro (NTT Human Interface Laboratories) VLSI Architecture of the I-Frame Encoder for the MPEG-2 Video Compression, A. Ngai (IBM) S3 Single Chip MPEG-1 Audio/Video Decoder, C. Steams (S3 Inc.) |
| Session 5 11:00-12:30 |
Graphics and Compression Chair: Shanker Singh (IBM)3D Graphics Processor Chip Set, M. Awaga (Fujitsu)
A Single Chip Video CD with Hi-Fi Audio for Consumer Applications, J. Fandrianto, B. Martin (Integrated Information Technology) Fast and Highly Reliable IBMLZ1 Compression Chip, J.M. Cheng, L.M. Duyanovich (IBM) |
| Session 6 14:00-16:00 |
Parallel and Vector Processing Chair: Alan Jay Smith, University of California, Berkeley Hot Compilers for Future Hot Chips, S.P. Amarisinghe, J.A. Anderson, R.S. French, M.W. Hall, M.S. Lam, S.W. Liao, B.R. Murphy, C.W. Tseng, C.S. Wilson (Stanford University) Scylla: A Memory Controller with Integrated Protocol Engines for Distributed Shared Memory Support, A. Nowatzyk, G. Aybay, M. Browne, S. Vishin (Sun Microsystems) The T0 Vector Microprocessor, K. Asanovic, J. Beck, B. Irissou, B.E.D. Kingsbury, N. Morgan, J. Wawrzynek (Univ. of California, Berkeley) A 150MHz Superscalar RISC Processor with Pseudo Vector Processing Feature, K. Saito, M. Hashimoto, K. Matsubara, H. Sawamoto, R. Yamagata, T. Kumagai, E. Kamada, T. Hotta, T. Nakano (Hitatchi); K. Nakazawa (University of Tsukuba) |
| Session 7 16:30-18:00 |
RISC (Part 2) Chair: Donald Alpert, Intel Corp.UltraSPARC™-1: A 64-bit Superscalar Processor with Multimedia Support, M. Tremblay (Sun Microsystems)
Smaller, Faster, Cooler… Evolving the PowerPC Family, D. Balser (Somerset Microprocessor Dev. Center, IBM) R10000 Superscalar Microprocessor, A. Ahi, A. Bodica, G. Shippen, H. Sucar, H. Su, J. Chuang, N. Vasseghi, R. Ramchandani, R. Martin, R. Conrad, Y. Chen, K. Yeager, W. Voegtli Jr., M. Seddighnezhad, Y. Van Atta (Silicon Graphics) |